1. Field of the Invention
The present invention relates to a process for forming an emitter of a bipolar transistor, and in particular, to a self-aligned process of forming a polysilicon emitter of a bipolar transistor that does not result in etching of the base upon which the emitter is formed.
2. Description of the Related Art
FIGS. 1A-1F show cross-sectional views of the conventional process steps for forming an NPN bipolar transistor having a polysilicon emitter.
FIG. 1A shows the starting point for the process. A high dose of N type dopant is implanted into silicon substrate 100 to create N+ region 102. Epitaxial silicon 101 is then grown from substrate 100 with adequate doping and thickness to meet the necessary collector requirements (BV.sub.ceo, BV.sub.cbo, etc.) of the particular device. Isolation structures 104 are formed using conventional techniques such as LOCOS or shallow trench isolation. Finally, sink 103 enabling electrical contact with the collector is formed by implantation of high doses of n type dopant at relatively low energy.
FIG. 1B shows the implant of p type dopant into epitaxial silicon 101 to form intrinsic base 106, followed by formation of polysilicon layer 108 on top of epitaxial silicon 101, sink 103, and isolation structures 104.
FIG. 1C shows the formation of a patterned photoresist mask 110 over the polysilicon layer 108. Photoresist mask 110 is present over the region in which the emitter will be formed.
FIG. 1D shows etching of unmasked polysilicon 108 to define polysilicon emitter structure 112. Here, the difficulty in selectively etching polysilicon versus underlying epitaxial silicon causes overetching of epitaxial silicon 101. This overetching produces recesses 114 in epitaxial silicon 100 between isolation structures 104. Sink 103 is also partially degraded by this overetching.
FIG. 1E shows implant of medium level doses (typically 1.times.10.sup.18 atoms/cm.sup.3) of p type dopant into epitaxial silicon adjacent to emitter 112, forming link base 118.
FIG. 1F shows the formation of emitter spacer structures 119, followed by the implant of high level doses (typically 1.times.10.sup.19 -1.times.10.sup.20 atoms/cm.sup.3) of p type dopant into the link base 118, forming extrinsic base 121.
Fabrication of the bipolar transistor 116 is finalized by creating silicided emitter, sink, and extrinsic base contacts, and an overlying interconnect metallization structure.
The conventional process flow shown in FIGS. 1A-1F can be successfully implemented to fabricate bipolar transistors. However, the conventional process suffers from several disadvantages.
Overetching of epitaxial silicon in the base discussed above in connection with FIG. 1D occurs because no plasma etching technology has yet been discovered which is selective to polysilicon over epitaxial silicon. Thus, all conventional fabrication processes must trade off polysilicon overetch in the base with product yield.
Specifically, too little polysilicon overetch results in possible shorting between the polysilicon emitter and the link base due to the presence of residual polysilicon on top of the link base.
Too much polysilicon overetch risks degradation of device characteristics. Specifically, overetching reduces the electronic connection between the intrinsic base and the link base, resulting in excessively high overall base resistance. Overetching also results in positioning of the link and extrinsic bases closer to the underlying silicon substrate, enhancing the possibility of leakage or breakdown between base and substrate. Moreover, overetching also results in loss of a portion of the sink region.
Therefore, there is a need in the art for a process of forming a bipolar transistor structure that eliminates overetching of silicon upon which the polysilicon emitter is formed, minimizing base resistance and allowing for creation of shallow base regions.